87
9152BINDCO02/10
ATA8743
19.4 Register Description
19.4.1
MCUCR MCU Control Register
" Bits 7, 2 Res: Reserved Bits
These bits are reserved bits in the ATtiny24/44/84 and will always read as zero.
" Bit 6 PUD: Pull-up Disable
When this bit is written to one, the pull-ups in the I/O ports are disabled even if the DDxn and
PORTxn Registers are configured to enable the pull-ups ({DDxn, PORTxn} = 0b01). See Con-
figuring the Pin on page 73 for more details about this feature.
19.4.2
PORTA Port A Data Register
19.4.3
DDRA Port A Data Direction Register
19.4.4
PINA Port A Input Pins Address
19.4.5
PORTB Port B Data Register
19.4.6
DDRB Port B Data Direction Register
Bit
7
6
5
4
3
2
1
0
PUD
SE
SM1
SM0
ISC01
ISC00
MCUCR
Read/Write
R
R/W
R/W
R/W
R/W
R
R
R
Initial Value
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
0x1B (0x3B)
PORTA7
PORTA6
PORTA5
PORTA4
PORTA3
PORTA2
PORTA1
PORTA0
PORTA
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
0x1A (0x3A)
DDA7
DDA6
DDA5
DDA4
DDA3
DDA2
DDA1
DDA0
DDRB
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
0x19 (0x39)
PINA7
PINA6
PINA5
PINA4
PINA3
PINA2
PINA1
PINA0
PINB
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
N/A
N/A
N/A
N/A
N/A
N/A
Bit
7
6
5
4
3
2
1
0
0x18 (0x38)
PORTB3
PORTB2
PORTB1
PORTB0
PORTB
Read/Write
R
R
R
R
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
0x17 (0x37)
DDB3
DDB2
DDB1
DDB0
DDRB
Read/Write
R
R
R
R
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
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